A sequential comparison type AD (Analog to Digital) conversion circuit which includes a small number of analog circuits and which can be realized by the use of comparatively simple circuits is known. A sequential comparison type AD conversion circuit is significantly consistent with a CMOS (Complementary Metal-Oxide Semiconductor) process and can be made minute. Accordingly, sequential comparison type AD conversion circuits are used for various purposes.
Conversion methods that are adopted in sequential comparison type AD conversion circuits are of two types: a clock synchronization type and a clock non-synchronization type. With a clock synchronization type conversion an AD conversion is made one bit for each clock of an external clock.
With a clock non-synchronization type conversion, on the other hand, an AD conversion of all bits is made by one clock of an external clock. With a clock non-synchronization type conversion, for example, time for which an external clock is at an H (High) level is sampling time for which an input signal is sampled and time for which the external clock is at an L (Low) level is AD conversion time for which the sampled input signal is AD-converted.
In order to secure AD conversion time, the technique of using an external clock signal the duty ratio of which is controlled so as to make L level time longer than H level time or the technique of controlling time for which an external clock is at an L level for making an AD conversion with desired resolution was formerly proposed.
Japanese Laid-open Patent Publication No. 2011-61597
However, sampling of an input signal ends before the elapse of set sampling time, depending on the characteristics of an AD conversion circuit or conditions under which the AD conversion circuit operates. As a result, there may be extra sampling time.